Tomeki

Explore Books on
timing circuits

1-24 of 46 Books

View Timing optimization through clock skew scheduling By Ivan S. Kourtev,Ivan S. Kourtev,Eby G. Friedman,Baris Taskin
Cover of Timing optimization through clock skew scheduling by ivan s. kourtev,ivan s. kourtev,eby g. friedman,baris taskin

Timing optimization through clock skew scheduling

By Ivan S. Kourtev,Ivan S. Kourtev,Eby G. Friedman,Baris Taskin

View Digital system clocking By Vojin G Oklobdzija,Vojin G. Oklobdzija,Vladimir M. Stojanovic,Dejan M. Markovic,Nikola M. Nedovic
Cover of Digital system clocking by vojin g oklobdzija,vojin g. oklobdzija,vladimir m. stojanovic,dejan m. markovic,nikola m. nedovic

Digital system clocking

By Vojin G Oklobdzija,Vojin G. Oklobdzija,Vladimir M. Stojanovic,Dejan M. Markovic,Nikola M. Nedovic

View IC timer cookbook By Walter G. Jung
Cover of IC timer cookbook by walter g. jung

IC timer cookbook

By Walter G. Jung

View Synchronization and arbitration in digital systems By David Kinniment
Cover of Synchronization and arbitration in digital systems by david kinniment

Synchronization and arbitration in digital systems

By David Kinniment

View Synchronization of digital telecommunications networks By Stefano Bregni
Cover of Synchronization of digital telecommunications networks by stefano bregni

Synchronization of digital telecommunications networks

By Stefano Bregni

View Constraining Designs for Synthesis and Timing Analysis By Sanjay Churiwala,Sridhar Gangadharan
Cover of Constraining Designs for Synthesis and Timing Analysis by sanjay churiwala,sridhar gangadharan

Constraining Designs for Synthesis and Timing Analysis

By Sanjay Churiwala,Sridhar Gangadharan

View Mobilitybased Time References For Wireless Sensor Networks By Fabio Sebastiano
Cover of Mobilitybased Time References For Wireless Sensor Networks by fabio sebastiano

Mobilitybased Time References For Wireless Sensor Networks

By Fabio Sebastiano

View Monolithic Phase-Locked Loops and Clock Recovery Circuits By Behzad Razavi
Cover of Monolithic Phase-Locked Loops and Clock Recovery Circuits by behzad razavi

Monolithic Phase-Locked Loops and Clock Recovery Circuits

By Behzad Razavi

View Processor-controlled timing module for Loran-C receiver By Robert W. Lilley

Processor-controlled timing module for Loran-C receiver

Processor-controlled timing module for Loran-C receiver

By Robert W. Lilley

View 555 timer applications sourcebook, with experiments By Howard M. Berlin
Cover of 555 timer applications sourcebook, with experiments by howard m. berlin

555 timer applications sourcebook, with experiments

By Howard M. Berlin

View Modeling Embedded Systems and SoC's By Axel Jantsch
Cover of Modeling Embedded Systems and SoC's by axel jantsch

Modeling Embedded Systems and SoC's

By Axel Jantsch

View Synchronization techniques for digital receivers By Umberto Mengali
Cover of Synchronization techniques for digital receivers by umberto mengali

Synchronization techniques for digital receivers

By Umberto Mengali

View Logic-timing simulation and the degradation delay model By Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia
Cover of Logic-timing simulation and the degradation delay model by manuel j. bellido,jorge juan chico,manuel valencia

Logic-timing simulation and the degradation delay model

By Manuel J. Bellido,Jorge Juan Chico,Manuel Valencia

View Electronic switching, timing, and pulse circuits By Joseph M. Pettit
Cover of Electronic switching, timing, and pulse circuits by joseph m. pettit

Electronic switching, timing, and pulse circuits

By Joseph M. Pettit

View Static Timing Analysis for Nanometer Designs By Rakesh Chadha
Cover of Static Timing Analysis for Nanometer Designs by rakesh chadha

Static Timing Analysis for Nanometer Designs

By Rakesh Chadha

View Clocking in Modern VLSI Systems By Thucydides Xanthopoulos
Cover of Clocking in Modern VLSI Systems by thucydides xanthopoulos

Clocking in Modern VLSI Systems

By Thucydides Xanthopoulos

View High-Speed Clock Network Design By Qing K. Zhu
Cover of High-Speed Clock Network Design by qing k. zhu

High-Speed Clock Network Design

By Qing K. Zhu

View Processor-controlled timing module for Loran-C receiver By Robert W Lilley

Processor-controlled timing module for Loran-C receiver

Processor-controlled timing module for Loran-C receiver

By Robert W Lilley

View Timing analysis and simulation for signal integrity engineers By Greg Edlund

Timing analysis and simulation for signal integrity engineers

Timing analysis and simulation for signal integrity engineers

By Greg Edlund

View Synchronization and Arbitration in Digital Systems By David J. Kinniment
Cover of Synchronization and Arbitration in Digital Systems by david j. kinniment

Synchronization and Arbitration in Digital Systems

By David J. Kinniment

View Statistical analysis and optimization for VLSI By Ashish Srivastava
Cover of Statistical analysis and optimization for VLSI by ashish srivastava

Statistical analysis and optimization for VLSI

By Ashish Srivastava

View Taĭmery By E. A. Kolombet

Taĭmery

Taĭmery

By E. A. Kolombet

View ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems By ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (2002 Monterey, Calif.)

ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

By ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (2002 Monterey, Calif.)

View Skew-tolerant circuit design By David Money Harris

Skew-tolerant circuit design

Skew-tolerant circuit design

By David Money Harris