An edition of SystemVerilog for Verification (2006)
SystemVerilog for Verification
A Guide to Learning the Testbench Language Features
By Chris Spear
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Publish Date
2012
Publisher
Springer US
Language
eng
Pages
510
Description:
subjects: Systems engineering, Circuits and Systems, Computer input-output equipment, Computers, Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Computer engineering, Computer-aided design, Electrical engineering, Verification, Integrated circuits, SystemVerilog (Computer hardware description language), Verilog (computer hardware description language), Object-oriented programming (computer science), Computer hardware description languages, Object-oriented programming (Computer science)