Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

An edition of Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits (1995)

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

By David M. Russinoff

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Publish Date

1995

Publisher

National Aeronautics and Space Administration, Langley Research Center,National Technical Information Service, distributor

Language

eng

Pages

Description:

subjects: Hardware description languages, VHSIC (Circuits), Mathematical models, Program verification (Computers), Protocol (Computers)